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* Organization: 128K x 8 bits * Sector Erase architecture - Four 32K x 8 sectors * Single 5.00.5V power supply for read/write operations * High speed 120/150 ns address access time * Low power consumption: - 30 mA maximum read current - 50 mA maximum program current - 1.5 mA maximum standby current - 1 mA maximum standby current (low power) * 10,000 write/erase cycle endurance * JEDEC standard write cycle commands - protects data from accidental changes * Program/erase cycle end signals: - Data polling - DQ6 toggle * Low VCC write lock-out below 3.2V * JEDEC standard packages and pinouts: - 32-pin DIP - 32-pin PLCC - 32-pin TSOP
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DQ0~DQ7 VCC VSS
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32-pin PDIP
Erase voltage switch Input/output buffers
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC* A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
32-pin PLCC
A12 A15 A16 NC VCC WE NC* A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21
AS29F010
WE
State control Command register Program voltage switch Data latch
AS29F010
CE OE
Chip enable Output enable Logic
A14 A13 A8 A9 A11 OE A10 CE DQ7
Address latch
Low VCC detector A0~A16
Program/erase pulse timer
Y-Decoder
Y-Gating
A11 A9 A8 A13 A14 NC WE VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-pin TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
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X-Decoder
1,048,576 bit Cell matrix
AS29F010
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AS29F010-120 Maximum access time Chip enable access time Output enable access time tAA tCE tOE 120 120 50 AS29F010-150 150 150 50 Unit ns ns ns
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Copyright (c)1998 Alliance Semiconductor. All rights reserved.
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The AS29F010 is a high performance 1 megabit 5 volt-only Flash memory organized as 128K bytes of 8 bits each. It is divided into four sectors of 32K bytes each. Each sector is separately erased and programmed without affecting data in the other sectors. All prog ram, erase, and verify operations are 5-volt only, and require no external 12V supply pin. All required features for in-system programmability are provided. The AS29F010 provides high performance with a maximum access time of 120, or 150 ns. Chip Enable ( CE), Output Enable (OE), and Write Enable (WE) pins allow easy interface with the system bus. Program, erase, and verify operations are controlled with an on-chip command register using a JEDEC standard Write State Machine approach to enter commands. Each command requires four write cycles to be executed. Address and data are latched internally during all write, erase, and verify operations, and an internal timer terminates each command. The chip has a typical timer period of 200 s for all commands but Erase, which has a typical period of 800 ms. Under nominal conditions, a sector can be completely programmed and verified in less than 12 seconds. To program, erase, and verify a sector typically takes less than 18 seconds. Data protection is provided by a low-VCC lockout and by error checking in the Write State Machine. DATA polling and Toggle Bit modes are used to show that the chip is executing a command when the AS29F010 is read during a write or erase operation. After Erase or P ogram commands,Verify-1 andVerify-0 command modes ensure sufficient margin for reliable operation. (See command summary on page 5.) The AS29F010 is packaged in 32-pin DIP, PLCC and TSOP packages with JEDEC standard pinouts for one megabit Flash memories.
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The array consists of 128K (131,072) bytes divided into four sectors of 32K bytes each. Addresses A15 and A16 select the four sectors:
Sector 0 1 2 3
Address range 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh
Address pins A0-A5 A6-A14 A15-A16
Function CA: Column addresses 00-3Fh RA: Row addresses 000-1FFh SA: Sector addresses 0-3h
The AS29F010 is shipped in the erased state with all bits set to 1. Programmed bits are set to 0. Data is programmed into the a ray one byte at a time. All programmed bits remain set to 0 until the sector is erased and verified using the SectorErase and Verify algorit hm. Erase returns all bytes in a 32K sector to the erased state FFh, or all bits set to 1. Each sector is erased individually with no effect on the other sectors.
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The AS29F010 is controlled by a Write State Machine (WSM) that interprets and executes commands. At power-up the WSM is reset to normal read mode. Once a command is initiated by writing data into the DQ pins with the WE pin, the WSM enters the command mode and keeps the chip powered up until the command is finished. After the command is terminated by the internal timer, the WSM returns to the normal read mode.
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Mode Read Output disable Standby Mfr. code Device code Write command
Key:
CE L L H L L L
OE L H H L L H
WE H H H H H L
A0 A0 X X L H A0
A9 A9 X X Vh Vh A9
DQ DOUT High Z High Z 52h CODE (03h,04h,06h) DIN
L =Low (VIH); Vh = 11.5-12.5V; X =Don't care
Read mode: Selected with CE and OE low, WE high. Data is valid tAA after addresses are stable, tCE after CE is low and tOE after OE is low. Output disable: Part remains powered up; but outputs disabled with OE pulled high. Standby: Part is powered down, and ICC reduced to 1.5 mA for TTL input levels (<1.0 mA for CMOS input levels). Mfr. (manufacturer) code, Device code: Selected by A9 = 11.5-12.5V. When CE and OE are pulled low the outputs are enabled and a data byte is read out. When A0 is pulled low the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high DOUT = 03h,04h, 06h, the Alliance device codes for the AS29F010. Write command: Selected by CE and WE pulled low, OE pulled high. Initiates command mode in the WSM and latches addresses and data into the chip. Once a write command starts, the WSM stays in command mode until the command is completed or it times out. Addresses are latched on the falling edge of WE and CE, whichever occurs later; data is latched on the rising edge o WE and CE, whichever occurs first. The WE signal is filtered to prevent spurious events from being detected as write commands.
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All commands require four bus write cycles to execute. After four write cycles the command is executed until terminated by the i nternal timer. For verify commands a read operation after Write[4] in a write command bus cycle reads out the data from thearray. For manufacturer and device code commands the ID code is read out. For other operations a read operation reads out a status byte on the outputs.
Address in Bus write[1] Bus write[2] Bus write[3] Bus write[4] Bus read 5555h 2AAAh 5555h Address in Address in
Data in AAh 55h Command code Data in DOUT
Command timeout: For each operation the address and data are latched at bus Write[4] and held until the operation completes and times-out. After time-out the WSM returns the AS29F010 to normal mode. Each individual operation requires the 4-cycle write command sequence to execute. The AS29F010 does not remain in command mode after time-out. When a command times-out only the error flag is not reset.
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Errors and timeout: Any of the following conditions sets the error flag.
* Any write command which does not match the sequence above for Write{1]. Write{2], and Write[3]. * Any write cycle that follows more than 150 s after the previous write cycle. * The command Data [3] in Write[3] has more than one bit set high. This indicates conflicting commands. * VCC drops below VLKO during command execution.
Once the error flag is set, the AS29F010 times out and returns to normal Readmode. The error flag remains until it is cleared by a reset command. The error flag can be read by executing a status command and reading the status byte.
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The Command Code table displays the bus cycles required for each command mode. Read delay is the minimum delay after Write [4] during a write command bus cycle before a valid read may be executed. Timeout indicates the maximum delay before the WSM returns the AS29F010 to normal mode. Erase has a longer timeout than the other modes. Status byte can be read almost immediately after a Write[4], but the verify commands require a 25 s delay to read valid data.
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Mode Reset Status ID Read code Verify-0 Verify-1 Converge Program Erase DIN[3] Write[3] data 00h 01h 02h 04h 08h 10h 40h 80h AIN[4] Write[4] address x x 0000h 0001h AIN AIN AIN AIN AIN DIN[4] data x x x x x x 00h DIN FFh Read address 0000h 0000h 0000h 0001h AIN AIN AIN AIN AIN Read data Status Status Mfr. code Device code DOUT DOUT Status Status Status Read delay 100 ns 100 ns 52h 100 ns 04h 100 ns 25 s 25 s 100 ns 100 ns 100 ns Maximum time out 250 s 250 s 250 s 250 s 250 s 250 s 250 s 1000 s
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Individual write commands are used together in eight program and erase algorithms to guarantee the AS29F010 operating margins for the life of the part. Refer to the AS29F010 Programming Specification for details on the algorithms for program and erase operation .
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Parameter Supply voltage Input voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.0 -0.5 Typ 5.0 0 -
+7D# #3&#WR#.:3&, Max 5.5 0 VCC + 1.0 0.8 Unit V V V V
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Parameter Input voltage (Input or DQ pin) Input voltage (A9 pin) Output voltage Power supply voltage Operating temperature Storage temperature (plastic) Short circuit output current Symbol VIN VIN VOUT VCC TOPR TSTG IOUT Min -1.0 -1.0 -1.0 +4.5 -55 -65 Max VCC + 1.0 +13.0 VCC + 1.0 +5.5 +125 +125 100 Unit V V V V C C mA
Latch-up current IIN 100 mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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20 ns 20 ns -2.0V VCC+2.0V VCC+0.5V +2.0V 20 ns 20 ns 20 ns +0.8V -0.5V 20 ns
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Parameter Input load current Output leakage current Output short circuit current Active current, read @ 6MHz Active current, program/erase Standby current Input: low level Input: high level Output low voltage Output high level Low VCC lock out voltage Input HV select voltage Symbol ILI ILO IOS ICC ICCPRG ISB1 (TTL) ICCPD VIL VIH VOL VOH1 VOH2 VLKO VID IOL = 12mA IOH = -2.5 mA IOH = -100 A Test conditions
+9&&# #813"3189/#966# #39/#7D# #3&#WR#.:3&, Min 0.5 2.0 2.4 VCC - 0.4 3.2 11.5 Max 1 1 100 30 50 1.5 1.0 2 0.8 VSS + 0.3 0.45 4.2 12.5 Unit A A mA mA mA mA mA A V V VIN = VSS to VCC, VSS = VMAX VOUT = VSS to VCC, VSS = VMAX VOUT = 0.5V CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIH RP = 0V
ISB2 (CMOS) CE = VCC
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1 2 3 Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second. OUT = 0.5V was selected to avoid test problems caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.) The ICC current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency component typically is less than 2 mA/MHz with OE at VIH. ICC active while program or erase operations are in progress.
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JEDEC symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std symbol tRC tACC tCE tOE tDF tDF tOH Parameter Read cycle time Address to output delay Chip enable to output Output enable to output Chip enable to output High Z Output enable to output High Z Output hold time from addresses, first occurrence of CE or OE
+9&&# #813"3189/#966# #39/#7D# #3&#WR#.:3&, -120 Min 120 0 Max 120 120 50 30 30 Min 150 0 -150 Max 150 150 50 30 30 Unit ns ns ns ns ns ns ns
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JEDEC symbol tAVAV tAVWL tWLAX tDVWH tWHDX Std symbol tWC tAS tAH tDS tDH tOES tOEH tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Output enable setup time Output enable hold time: Read Output enable hold time: Toggle and DATA polling Read recover time before write CE setup time CE hold time Write pulse width Write pulse width high Programming pulse time Erase pulse time VCC setup time
+9&&# #813"3189/#966# #39/#7D# #3&#WR#.:3&, -120 Min 120 0 50 50 0 0 0 10 0 0 0 80 20 250 1000 2 Max Min 150 0 50 50 0 0 0 10 0 0 0 80 20 250 1000 2 -150 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s
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Addresses CE tOF OE WE tOE tCE tACC Outputs High Z tPWH enabled valid data out High Z tOH tRC stable
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tWPH Addresses tCS CE tOES OE tWP WE tDH tDS Outputs High Z data in High-Z tAS tAH
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Write[1] Addresses AIN[1] = 5555h CE OE WE Outputs DIN[1] = AAh DIN[2] = 55h DIN[3] = Com. DIN[4] = DIN DOUT AIN[2] = 2AAAh AIN[3] = 5555h AIN[4] = AIN AIN Write[2] Write[3] Write[4] Read
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For all waveforms, AIN[4:1], and DIN[4:1] = Address and Data for write cycles 1-4; DIN = Data to be programmed at address AIN; Com. = Command byte input on the DQ pins during Write[3]; DOUT = Status byte, Manufacturer ID code, or array data for verify.
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+5V 1N3064 or equivalent Device under test 100 pF* 6.2K 1N3064 or equivalent GND GND 2.7K
GND *including scope and jig capacitance
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Parameter Input voltage with respect to VSS on pin A9 Input voltage with respect to VSS on all DQ pins Current
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
Min -1.0 -1.0 -100
Max +13.5 VCC+1.0 +100
Unit V V mA
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Symbol CIN COUT CIN2 Parameter Input capacitance Output capacitance Control pin capacitance Test setup VIN = 0 VOUT = 0 VIN = 0 Typical 6 8.5 7.5
+|# #4#0+]/#7D# #58&, Max 7.5 12 9 Unit pF pF F
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Symbol
CIN
+|# #4#0+]/#7D# #58&, Test setup VIN = 0 VOUT = 0 VIN = 0 Typical 4 8 8 Max 6 12 12 Unit pF pF F
Parameter Input capacitance Output capacitance Control pin capacitance
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COUT CIN2
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Parameter
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-
Typical 6.0 48 10,000 200 200
Max 8.2 8.2 80 250 250
Unit sec sec sec cycles s s
Sector erase and Verify-1 time (excludes 00h programming prior to erase) Sector programming time Chip programming time Erase program cycles Byte program time Byte verify-0 time
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Parameter Minimum pattern data retention time Temperature 150 125 Min 10 20 Unit years years
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Package \ Access time Plastic DIP, 600 mil, 32-pin PLCC, 0.55 x 0.45'' 32-pin TSOP, 8x20 mm, 32-pin 120 ns AS29F010-120PC AS29F010-120LC AS29F010-120TC 150 ns AS29F010-150PC AS29F010-150LC AS29F010-150TC
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AS29F Flash EEPROM prefix 010 Device number -XXX Address access time X Package: P = PDIP L = PLCC T = TSOP C Commercial temperature range, 0C to 70 C
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